1. Field of the Invention
The present invention relates to CMOS integrated circuits and, more particularly, to a circuit for establishing a prescribed threshold voltage and for controlling the threshold voltage of one or more CMOS circuits in an integrated circuit to mitigate the effects of process variations, temperature variations, and other factors that may cause the threshold voltage to vary.
2. Description of the Prior Art
CMOS integrated circuits are widely known in the electronics industry. Although "MOS" is an acronym for metal oxide semiconductor, conductive polysilicon gate transistors are now more common than metal gate transistors. As used herein, the acronym "MOS" refers generally to conductor oxide semiconductor devices wherein the gate may be metal, conductive polysilicon, or any other conductor.
The MOS transistors that are utilized in such integrated circuits are characterized by threshold gate-to-source voltage required for the transistor to turn on and to conduct drain current. The threshold voltage is susceptible to manufacturing process variations and temperature variations. In many cases, threshold voltage variations are tolerable. In other cases, however, such threshold voltage variations are detrimental to circuit performance. For example, when the inputs to a MOS integrated circuit must be compatible with TTL logic or some other logic family, threshold voltages must be maintained within the limits of the logic family. It is known that the threshold voltages of all MOS devices on an integrated circuit tend to be matched to track each other, since they are subject to the same temperature variations in the same manufacturing process.
In the past, threshold voltages of MOS circuits have been controlled by relatively complex circuitry. For example, an on-chip variable voltage supply may be utilized since the circuit threshold voltage varies with the supply voltage. Such prior art techniques have not been satisfactory since the circuitry occupies a significant part of the chip area, requires significant current for operation, and tends to be difficult to stabilize.
Another prior art approach involved providing a single feedback loop for PMOS transistors. However, this approach proved to be relatively inefficient.
For proper operation, logic circuits must have sufficient static noise margins for high and low logic levels: V.sub.nm, l =V.sub.th, 1 -V.sub.ol and V.sub.nm, h =V.sub.o, h -V.sub.th, h. In CMOS output levels: V.sub.o,l =V.sub.ss and V.sub.o, h =V.sub.dd. This is why the values V.sub.nm, l and V.sub.nm, h are determined by a switching threshold V.sub.th of the static transfer characteristic (at the threshold point V.sub.out =V.sub.in =V.sub.th). Switching threshold V.sub.th depends not only on the threshold voltages V.sub.t of NMOS and PMOS transistors, but on their effective transconductances and saturation voltages, and on the complexity (the number of simultaneously switched inputs) of the logic circuit. For a power supply V.sub.dd &lt;1V switching threshold depends on the subthreshold slope also.
The chip-to-chip process variations of transistor parameters, as well as temperature and supply voltage variation reduce the noise margins.
For the supply voltages V.sub.dd &gt;2V the projected values V.sub.tn and V.sub.tp usually make up 15% to 20% of V.sub.dd. This ensures proper operation of the logic circuits made of wide libraries of logic elements with regard to the V.sub.t process variations and V.sub.t variation from temperature. The V.sub.t process variations can achieve 0.2V. V.sub.t variations in the temperature range from 0 to 100.degree. C. may increase up to 0.4V.
Under these V.sub.t variations, when V.sub.dd decreases to 1V and below, the restrictions of the performance and noise immunity losses require stabilization of the switching thresholds of the logic circuits.